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xSPI (8x SPI)
SPI, Dual, Quad
1.8V, 3.0V. Wide VCC
Ultra-low Energy, Low Power
Known Good Die program
Up to 125°C operating temperature
All voltage levels
- Wide Voltage 1.65V to 3.6V
Renesas Memory Products
1 month ago
AT25SL321 Simulation Model ClarificationPosted by aeva 15 points 2 replies
I would like to seek clarification with the reset behaviour of the Verilog simulation model provided for the AT25SL321 SPI Flash device please.
The behaviour I wish to check is that of QPI Mode upon device reset. The datasheet states "..after software reset using the Reset (99h) instruction, the default state of the device is Standard/Dual/Quad SPI mode".
This, we interpret to mean that QPI mode is disabled by a software reset. The Quad Enable bit in Status Register-2 is non-volatile, so this would remain set but the Flash should be accessed with SPI instructions immediately after Reset.
The Verilog model has different behaviour (RTL snippet attached). Here, the QPI mode is retained after software reset because the Status Register-2 Quad Enable (QE) bit sets QPI_Mode directly in the reset procedure. For this to match the interpreted behaviour (and that seen in other Dialog memory devices) QPI_Mode should be set to 0 in the RST_Event process instead.
Is the model wrong or did I interpret the datasheet incorrectly?