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SLG4DVKADV

GreenPAK Advanced Development Board

adv_development_platform.png

Working in tandem with the GreenPAK Designer software, GreenPAK Advanced Development Board allows designers to:

  • Program custom samples in minutes
  • Test GreenPAK projects in-circuit
  • Develop using any GreenPAK device

Features

USB interface

MacOS, Windows and Linux compatible

Programming and Emulation

Gated expansion header for connection to external test equipment

Integrated signal and logic generators

LEDs for visual indication

Kit Contents

Advanced Development Board

USB cable

Quick Start Guide

Please note: Socket Adapters should be ordered separately.

Compatible Devices

SLG46xxxx-SKT (Socket Kit - includes Socket Adapter and 50 Samples)

SLG4SAxx-xxXxx (Socket Adapter)

SLG4TAxx-SLG46xxx (Training Adapter Board)

SLG46xxxx (Samples)

GreenPAK Designer (included in Go Configure™Software Hub)
Name Date Version
Go Configure™Software Hub for Windows, macOS or Linux(7.58 KB)
User guides and manuals
Name Date Version
Advanced Development Kit Quick Start Guide (249.34 KB) 11/09/2020 1.2
GreenPAK Advanced Development Platform User Guide (2.66 MB) 14/09/2021 2.3
Video thumbnail, click to open and play

GreenPAK Configurable Mixed-signal IC Introduction

Video thumbnail, click to open and play

GreenPAK Designer Software

Video thumbnail, click to open and play

GreenPAK Development Platform

Video thumbnail, click to open and play

Choosing the Right GreenPAK

View the full list of the GreenPAK videos in our Training Video Library.

GreenPAK Development Board

Provides full programming, emulation and testing functions for GreenPAK devices. For use with SLG46xxxX-SKT sockets kits.

Working in tandem with the GreenPAK Designer software, GreenPAK Advanced Development Board allows designers to:

  • Program custom samples in minutes
  • Test GreenPAK projects in-circuit
  • Develop using any GreenPAK device
Suitable for:
  • Programming
  • Emulation
  • Signal and Logic Generators
Features:
  • USB interface
  • MacOS, Windows and Linux compatible
  • Programming and Emulation
  • Gated expansion header for connection to external test equipment
  • Integrated signal and logic generators
  • LEDs for visual indication
GreenPAK Advanced Development Board
This item is out of stock.
$99.00
greenpak_32_pinadapter.png

32-pin to 20-pin adapter for SLG468x development on SLG4DVKADV

SLG4AB2
$10.00
SLG4DVKINTRO Kit Revised

GreenPAK Introduction Kit. Included are: SLG4DVKADV (GreenPAK Advanced Development Board), SLG4SA-DIP (Adapter for GreenPAK Advanced Development Board) , two each of the following DIP Proto Boards (SLG46120V-DIP, SLG46721V-DIP, SLG46620V-DIP, SLG46537V-DIP, SLG46826V-DIP) and USB cable.

SLG4DVKINTRO
$79.00
SLG4TA20SP SLG46826

Training Adapter Board for SLG46826.

SLG4TA20SP-SLG46826
$12.00
slg4sa8-10x12.jpg

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • STQFN-8 (1.0 x 1.2 mm) GreenPAK
SLG4SA8-10x12
$20.00
SLG4SA20 20x30

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • MSTQFN-29 (3.0 x 3.0 mm) GreenPAK
SLG4SA29-30x30
$20.00
SLG4SA12 16x16

Socket adapter. For use with :

  • GreenPAK Advanced Development Board
  • STQFN-12 (1.6 x 1.6 mm) GreenPAK
SLG4SA12-16x16
$20.00
SLG4SA12DS 16x16

Socket adapter. For use with :

  • GreenPAK Advanced Development Board
  • STQFN-12 (1.6 x 1.6 mm) Dual Supply GreenPAK
SLG4SA12DS-16x16
$20.00
SLG4SA14 16x20

Socket adapter. For use with :

  • GreenPAK Advanced Development Board
  • STQFN-14 (1.6 x 2.0 mm) GreenPAK
SLG4SA14-16x20
$20.00
SLG4SA14 16x25

Socket adapter. For use with :

  • GreenPAK Advanced Development Board
  • STQFN-14 (1.6 x 2.5 mm) GreenPAK
SLG4SA14-16x25
$20.00
SLG4SA14 20x22

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • STQFN-14 (2.0 x 2.2 mm) GreenPAK
SLG4SA14-20x22
$20.00
SLG4SA14DS 20x22

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • STQFN-14 (2.0 x 2.2 mm) Dual Supply GreenPAK
SLG4SA14DS-20x22
$20.00
SLG4SA16 16x20

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • MSTQFN-16 (1.6 x 2.0 mm) GreenPAK
SLG4SA16-16x20
$20.00
SLG4SA16LL

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • MSTQFN-16 (1.6 x 1.6 mm) GreenPAK
SLG4SA16LL-16x16
$20.00
SLG4SA20 20x30

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • STQFN-20 (2.0 x 3.0 mm) GreenPAK
SLG4SA20-20x30
$20.00
SLG4SA20DS 20x30

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • STQFN-20 (2.0 x 3.0 mm) Dual Supply GreenPAK
SLG4SA20DS-20x30
$20.00
SLG4SA22 20x22

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • MSTQFN-22 (2.0 x 2.2 mm) Dual Supply GreenPAK
SLG4SA22-20x22
$20.00
SLG4SA22 20x22

Socket adapter. For use with:

  • GreenPAK Advanced Development Board
  • MSTQFN-22 (2.0 x 2.2 mm) Dual Supply GreenPAK
SLG4SA22DS-20x22
$20.00
SLG4SA-DIP

GreenPAK DIP Adapter for GreenPAK Advanced Development Board. Allows the use of the SLG46xxxV-DIP Proto boards with the GreenPAK Advanced Development Board. Acts as the bridge between Advanced and DIP Development Platforms.

SLG4SA-DIP
$2.00
Back to results

GreenPAK and GreenFET

2 months ago

SLG46536 errata

Posted by devgit 130 points 6 replies
0 upvotes

Hello,

I am developing the SLG46536 for a new product and testing this on the "GreenPAK Advanced Development Platform".

There is an errata for this chip: regarding item #6 "3.6.2 Conditions When IO Latching is Enabled" and I have a query regarding this :-

I have a project that uses just the I2C block/module/macro, with its 8 outputs connected to 8 output pins (for generic GPIO output pin expansion)

In the Greenpak design, I have not enabled "IO latching", yet the output pins latch perfectly, and do not appear to be affected by this errata.I have other none Greenpak devices sharing the same I2C bus, no glitches can be detected on the SLG46536 output pins.

So my queries are :-

Has this errata been fixed for this chip?

Does the errata refer to something else other than the I2C block (this example shows an oscillator output pin which is confusing)

Using the "GreenPAK Advanced Development Platform" Does the "Test mode" (this chip has been programmed) use the actual chip, or is is partly emulated? (IE is this a real world test!)

Regards

 

John.
 

2 months ago

olehs

 Hi devgit

Thank you for your appeal, 

If you don't use the "IO latching" option, you don't need to worry about this. This issue can be reflected only when "IO latching" is enabled. 

When you are using Test Mode Advanced Dev Board only applies VDD to the chip, it doesn't write anything to it unless you use the I2C generator to change the register. Emulation meanwhile send the data to the register without programming 

Best regards, 

Oleh Sapiha

 

2 months ago

Hi Oleh,

 

Thanks for your reply. Sounds good, but I would be interested to know what the "IO latching" option actually does. Is this documented?

 

Regards

 

John.

2 months ago

olehs

Hi devgit,

If IO Latching is Enabled, the GPIO outputs will be held logic 1 or logic 0 during I2C activity, however, configuration bits will still update at the end of each acknowledge.
For an I2C Read, the GPIOs are Latched from the Start bit to the end of the Slave Address. For an I2C Write, the GPIOs are Latched from the Start bit to the Stop Bit. If IO Latched is Disabled, the GPIO outputs will not be held at a logic high or low. Configuration bits will update at the end of each Acknowledge.

Please take into account that IO latching doesn't work in Emulation Mode. The bit corresponding to IO latching can be changed during programing. 

Best regards, 

Oleh Sapiha

2 months ago

Hi Oleh,

Yes thanks I had read all of that information, but the errata was not very specific to me (and I am a newbie to these devices, sorry!). Looking again at the example on page 12 in the errata :-

https://www.dialog-semiconductor.com/sites/default/files/slg4653x_errat…

it shows the I2C cell outputs not connected to anything and 1 GPIO connected from an oscillator output.

So I am guessing from that example, that the "IO latching" enabled is refering to when using the I2C cell to address the registers on the chip that control GPIO's ?. So if you wrote to series of registers to set/reset the bits for GPIO outputs, the pins would all be latched and change state together at the end of the register writes sequence?

I am also guessing that this does not apply to my case, where I have connected the I2C cell's 8 outputs directly to the pins. So in this case, as it is just one virtual register write for all 8 bits, it does not need IO latching. Does that make sense?

Regards

 

John.

 

 

2 months ago

olehs

devgit, 

Yes, you are right when IO latching option is enabled, PINs will be latched during the I2C command, it refers not only to the PINs you will control via I2C but to all PINs. PINs will change their states after the ACK bit. 

If you are working on an I2C expander using the I2C block and its internal register, you don't need to latch the outputs at all.

Best regards, 

Oleh Sapiha 

 

2 months ago

Hi Oleh,

Thats great, thanks for your help.

Regards

John.