Skip to main content

SLG46827-A

Automotive GreenPAK™ Programmable Mixed-signal Matrix with In-System Programmability

SLG46827-A Block Diagram

17-GPIO, 4 ACMPs, I2C, 19 LUTs (max.), 8 CNT/DLY (max.), 17 DFF/LATCH (max.) and other Macrocells

The SLG46827-A provides a small, low power component for commonly used mixed-signal functions. The user creates the circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the IOs and the macrocells of the SLG46826. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit.

Lifecycle status

● Active

Macrocells Overview

Two High Speed General Purpose Rail-to-Rail Analog Comparators (ACMPxH);

Two Low Power General Purpose Rail-to-Rail Analog Comparators (ACMPxL);

Two Voltage References (Vref)

  • Two Vref Outputs; 

Eleven Combination Function Macrocells:

  • Three Selectable DFF/Latch or 2-bit LUTs;
  • One Selectable Programmable Pattern Generator or 2-bit LUT;
  • Six Selectable DFF/Latch or 3-bit LUTs;
  • One Selectable Pipe Delay or Ripple Counter or 3-bit LUT;

Eight Multi-Function Macrocells:

  • Seven Selectable DFF/Latch or 3-bit LUTs + 8-bit Delay/Counters;
  • One Selectable DFF/Latch or 4-bit LUT + 16-bit Delay/Counter;

Serial Communications:

  • I2C Protocol Interface;

Programmable Delay with Edge Detector Output;

Deglitch Filter with Edge Detector;

Three Oscillators (OSC):

  • 2.048 kHz Oscillator;
  • 2.048 MHz Oscillator;
  • 25 MHz Oscillator;

Analog Temperature Sensor;

Power On Reset (POR).

Features

In-System-Debug Feature

Multiple Time Programmable Memory In Development

Wide Range Power Supply

  • 2.5 V (±8%) to 5 V (±10%) VDD 
  • 1.8 V (±5%) to 5 V (±10%) VDD2 (VDD2 ≤ VDD

RoHS Compliant / Halogen-Free

AEC-Q100 Grade 2

Applications

In-Vehicle Navigation

Infotainment

Advanced Driver Assistance Systems (ADAS)

Automotive Display Clusters

Body Electronics

Packages and Ordering

SLG46827-AG: TSSOP-20 (6.5 x 6.4 x 1.2 mm, 0.65 mm pitch)

The product ID suffix indicates the package style.

Stay connected

Get in touch with us directly through our worldwide sales offices, or contact one of our global distributors and representatives.

Inquiries Distributors and Representatives Register for newsletters
Datasheets
Name Date Version
SLG46827-A Datasheet (2.54 MB) 24/02/2021 3.2
Errata
Name Date Version
SLG46827-A Errata (520.65 KB) 31/03/2021 1.2
User guides and manuals
Name Date Version
GSD Quick Start Guide (181.06 KB) 23/10/2020 1.0
RoHS and Reach
Name Date Version
Dialog Environmental Statement for IC Products (1.06 MB)
Video thumbnail, click to open and play

GreenPAK Configurable Mixed-signal IC Introduction

Video thumbnail, click to open and play

GreenPAK Designer Software

Video thumbnail, click to open and play

GreenPAK Development Platform

Video thumbnail, click to open and play

Choosing the Right GreenPAK

Video thumbnail, click to open and play

GreenPAK I2C

Video thumbnail, click to open and play

GreenPAK SPICE Introduction

View the full list of the GreenPAK videos in our Training Video Library.

This product is available in one package:

SLG46827-AG: TSSOP-20 (6.5 x 6.4 x 1.2 mm, 0.65 mm pitch)


Development board selector

GreenPAK Development Board

Provides full programming, emulation and testing functions for GreenPAK devices. For use with SLG46xxxX-SKT sockets kits.

Working in tandem with the GreenPAK Designer software, GreenPAK Advanced Development Board allows designers to:

  • Program custom samples in minutes
  • Test GreenPAK projects in-circuit
  • Develop using any GreenPAK device
Suitable for:
  • Programming
  • Emulation
  • Signal and Logic Generators
Features:
  • USB interface
  • MacOS, Windows and Linux compatible
  • Programming and Emulation
  • Gated expansion header for connection to external test equipment
  • Integrated signal and logic generators
  • LEDs for visual indication
GreenPAK Advanced Development Board
This item is out of stock.
$99.00
Recommended add-on:
SLG46827AG-SKT
$35.00
DIP

Perfect for breadboarding and fast prototypes.

Working in tandem with the GreenPAK Designer software, GreenPAK DIP Development Board allows designers to:

  • Program custom samples in minutes
  • Test GreenPAK projects in-circuit
Suitable for:
  • Programming
  • Emulation
Features:
  • USB interface
  • MacOS, Windows and Linux compatible
  • Programming and Emulation
  • Gated expansion header for connection to external test equipment
GreenPAK DIP Development Board
$29.99
SLG4DVKISP

GreenPAK Development Board for Serial Debugging and In-System Programmability.

  • Can support serial debugging for all GreenPAK parts with I²C
  • Serial programming for SLG46824, SLG46826, and SLG47004
  • Very helpful in late stages of development when doing debug on-board is easiest
GreenPAK Serial Debugger Board (GSD)
This item is out of stock.
$28.75
GreenPAK Development Board

GreenPAK Advanced Development Board

Provides full programming, emulation and testing functions for GreenPAK devices.
  • Programming
  • Emulation
  • Signal and Logic Generators
GreenPAK Advanced Development Board
This item is out of stock.
$99.00
Recommended add-on:
SLG46116V-SKT
$35.00
DIP

GreenPAK DIP Development Board

Perfect for breadboarding and fast prototypes.

Working in tandem with the GreenPAK Designer software, GreenPAK DIP Development Board allows designers to:

  • Program custom samples in minutes
  • Test GreenPAK projects in-circuit
  • Programming
  • Emulation
GreenPAK DIP Development Board
$29.99
Recommended add-on:
SLG46116V-DIP
$1.25
SLG4DVKISP

GreenPAK Serial Debugger Board (GSD)

GreenPAK Development Board for Serial Debugging and In-System Programmability.

  • Can support serial debugging for all GreenPAK parts with I²C
  • Serial programming for SLG46824, SLG46826, and SLG47004
  • Very helpful in late stages of development when doing debug on-board is easiest
GreenPAK Serial Debugger Board (GSD)
This item is out of stock.
$28.75

Other components

SLG46827-A

Programmable Mixed-signal Matrix. VDD1 = 2.3 to 5.5V VDD2 = 1.71-5.5V. 15-GPIO, 4 ACMP, 11 LUTs, 8 Multi-functional Macrocells, and other Counter/Delay/FF Macrocells. Package: TSSOP-20.

Price table:

Qty 100+
Price $0.60
SLG46827-A (un-programmed)

Note: All parts will be shipped in tape form.

$0.60
SLG46827-A

Programmable Mixed-signal Matrix. VDD1 = 2.3 to 5.5V, VDD2 = 1.71 to 5.5V. 15-GPIO, 4 ACMP, 11 LUTs, 8 Multi-functional Macrocells, and other Counter/Delay/FF Macrocells. Package: TSSOP-20.

SLG46827-A (programmed)

Note: All parts will be shipped in tape form.

$0.60
TSSOP-20n2

Included are: SLG4SA20-65x64 socket adapter, 50 SLG46827A samples.

SLG46827AG-SKT
$35.00
Back to results

GreenPAK and GreenFET

2 months ago

SLG46536 errata

Posted by devgit 130 points 6 replies
0 upvotes

Hello,

I am developing the SLG46536 for a new product and testing this on the "GreenPAK Advanced Development Platform".

There is an errata for this chip: regarding item #6 "3.6.2 Conditions When IO Latching is Enabled" and I have a query regarding this :-

I have a project that uses just the I2C block/module/macro, with its 8 outputs connected to 8 output pins (for generic GPIO output pin expansion)

In the Greenpak design, I have not enabled "IO latching", yet the output pins latch perfectly, and do not appear to be affected by this errata.I have other none Greenpak devices sharing the same I2C bus, no glitches can be detected on the SLG46536 output pins.

So my queries are :-

Has this errata been fixed for this chip?

Does the errata refer to something else other than the I2C block (this example shows an oscillator output pin which is confusing)

Using the "GreenPAK Advanced Development Platform" Does the "Test mode" (this chip has been programmed) use the actual chip, or is is partly emulated? (IE is this a real world test!)

Regards

 

John.
 

2 months ago

olehs

 Hi devgit

Thank you for your appeal, 

If you don't use the "IO latching" option, you don't need to worry about this. This issue can be reflected only when "IO latching" is enabled. 

When you are using Test Mode Advanced Dev Board only applies VDD to the chip, it doesn't write anything to it unless you use the I2C generator to change the register. Emulation meanwhile send the data to the register without programming 

Best regards, 

Oleh Sapiha

 

2 months ago

Hi Oleh,

 

Thanks for your reply. Sounds good, but I would be interested to know what the "IO latching" option actually does. Is this documented?

 

Regards

 

John.

2 months ago

olehs

Hi devgit,

If IO Latching is Enabled, the GPIO outputs will be held logic 1 or logic 0 during I2C activity, however, configuration bits will still update at the end of each acknowledge.
For an I2C Read, the GPIOs are Latched from the Start bit to the end of the Slave Address. For an I2C Write, the GPIOs are Latched from the Start bit to the Stop Bit. If IO Latched is Disabled, the GPIO outputs will not be held at a logic high or low. Configuration bits will update at the end of each Acknowledge.

Please take into account that IO latching doesn't work in Emulation Mode. The bit corresponding to IO latching can be changed during programing. 

Best regards, 

Oleh Sapiha

2 months ago

Hi Oleh,

Yes thanks I had read all of that information, but the errata was not very specific to me (and I am a newbie to these devices, sorry!). Looking again at the example on page 12 in the errata :-

https://www.dialog-semiconductor.com/sites/default/files/slg4653x_errat…

it shows the I2C cell outputs not connected to anything and 1 GPIO connected from an oscillator output.

So I am guessing from that example, that the "IO latching" enabled is refering to when using the I2C cell to address the registers on the chip that control GPIO's ?. So if you wrote to series of registers to set/reset the bits for GPIO outputs, the pins would all be latched and change state together at the end of the register writes sequence?

I am also guessing that this does not apply to my case, where I have connected the I2C cell's 8 outputs directly to the pins. So in this case, as it is just one virtual register write for all 8 bits, it does not need IO latching. Does that make sense?

Regards

 

John.

 

 

2 months ago

olehs

devgit, 

Yes, you are right when IO latching option is enabled, PINs will be latched during the I2C command, it refers not only to the PINs you will control via I2C but to all PINs. PINs will change their states after the ACK bit. 

If you are working on an I2C expander using the I2C block and its internal register, you don't need to latch the outputs at all.

Best regards, 

Oleh Sapiha 

 

2 months ago

Hi Oleh,

Thats great, thanks for your help.

Regards

John.