Overview

The FCI FC8050Q chip is a highly integrated device for Terrestrial Digital Multimedia Broadcasting (T-DMB). FC8050Q has all of the performance needed to enable the full range of T-DMB applications. It consists of two main blocks, the RF tuner and channel decoder.

The RF block supports single-band (Band-III). It is a highly integrated component working with a single 1.2V power supply. Because direct-conversion architecture is used in the RF block, additional components such as a bulky IF SAW filter and other IF matching components are no longer required. For the direct-conversion, it has a low noise fractional-N type frequency synthesizer and VCO. The RF block contains a Low Noise Amplifier (LNA), down-conversion mixer, Channel Selection Filter (CSF), and LO distribution network for Band-III.

The baseband block (BB) is an integrated circuit that provides a channel decoder for Digital Multimedia Broadcasting (DMB) signals based on ETS 300 401 (EUREKA-147). It is also in compliance with the function of Korea DAB/DMB (TTAS.KO -07.0024 and TTAS.KO-07.0026) standard. It contains a 10-bit Analog-to-Digital Converter (ADC) for IF input, OFDM demodulator, Reed Solomon decoder, and convolutional de-interleaver for providing forward error correcting. For audio data, it uses an MPEG I/II Layer II (MUSICAM) algorithm. It provides HPI, EBI2 LCD Interface of Qualcomm QSC series modem chip, SPI and I2C as a HOST interface. When it is used, I2C is the host interface, serial TS interface is also supported.

FC8050 Block Diagram
FC8050 Block Diagram
  • DAB (Eureka 147)/Korean DMB (TTAS.KO-07.0024 & TTAS.KO-07.0026) standard compliant receiver system-on-chip
  • DAB OFDM demodulator and channel decoder
    • Supports all DAB functions and modes (I, II, III, and IV) and Automatic Mode Detection (AMD)
    • Full data rate of 1.8Mbit can be decoded
    • Automatic frame/timing synchronization and fast channel re-acquisition
    • Demodulation and decoding of up to 64 sub-channels (UEP/EEP)
    • TII decoder
    • Automatic multiplex re-configuration
  • Host interfaces
    • Parallel interface: 3-bit control pins, 2-bit address/8-bit data bus, or 8-bit data bus compatible with Qualcomm QSC series modem chip
    • Serial interface: SPI and I2C
    • Support max. 8 services (audio, video and data stream)
    • MPEG-2 serial-TS output with various TS clocks (1.024MHz ~ 38.4MHz)
    • Be able to decode 2 video data with RS encoded stream
  • Electrical Characteristics
    • Embedded DC/DC and LDO
    • Supply voltages: 1.2V for core and 1.8/2.5/3.3V for I/O
    • Low power consumption: 34mW
    • Support various external clock 16.384/19.2/24.576/27/38.4MHz
    • Frequency band: Band-III (170MHz ~ 240MHz)
    • RX sensitivity -103.0dBm, adjacent channel sensitivity 50dB, far-off sensitivity 55dB
  • Package size: 6.0mm x 6.0mm 48-pin QFN

Applications

  • RF + BB SoC for T-DMB

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

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    FC8050Q
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