GreenPAK™ with Asynchronous State Machine (ASM)

GreenPAK™ with Asynchronous State Machine (ASM)

GreenPAK™ family devices that include the Asynchronous State Machine (ASM) macro-cell allow the user to develop their own custom state machine designs. The user has the option to set the definition of the states, the definition of allowed state transitions, and the definition of the signals that will trigger each state transition. This macro-cell can also be flexibly connected to I/O pins and other GPAK resources for state transition inputs, and outputs from the macro-cell can be routed to other resources or I/O pins. Two important performance parameters for this macro-cell are transition times of less than 1 µS from state to state, and a standby current of less than 1µA when not in active state transition.

This ASM macro-cell is supported in a new ASM Editor window in GPAK Designer SW. Shown here is the view inside the ASM editor. This editor supports the flexibility to:

  • Check boxes to select states in project, up to the allowable maximum number of states based on silicon architecture
  • Edit state names to match application
  • Easy “point and click” actions to add state transitions
  • Arrange state diagram for best comprehension
  • Set value of output signals in Output RAM Array

Inside the main GPAK Designer GUI, the ASM macro-cell shows up with inputs that drive state transitions, and outputs that can be routed to other internal resources, or out to pins. Inside each state, the allowed “next states” show up here, with an input that when asserted will cause that state transition to happen. The connection between resources used to make state transitions, and the state transition links is also shown back in the original ASM Editor window with labels on each of the state transition signals showing the source of the signal.

As this macro-cell does not require a clock input, it will consume less than one µA when not in active state transition. This gives the designer tremendous flexibility to create low power designs in minutes. This is especially valuable when designing event driven systems that are waiting long periods of time with little activity, as the ASM macro-cell can remain in a low power state waiting for input, and and react in less than a µS to change state.

PN Special Feature GPIO Nominal VDD
(V)
ADC ACMP DCMP Max. CNT/DLY Max. LUTs Max. DFF Pipe
Delay
Progr. DLY OSC Com. Interface Size (mm) Documents
                               
SLG46127
SLG46127MTR
2x P-FET 6 1.8 - 5.0 - 2 0 4 10 4 8-stage 1 RC OSC - MSTQFN-16 1.6 x 2.0 mm Documentation
SLG46580 ASM LDO 9 2.5 - 5.0 - 4 0 5 16 9 16-stage 1 Conf. OSCLP OSC I²C STQFN-20 2.0 x 3.0 mm Documentation
SLG46533
SLG46533MTR
- 18 1.8 - 5.0 - 4 0 7 25 15 16-stage 1 Conf. OSC Ring OSC Crystal OSC I²C MSTQFN-22 2.0 x 2.2 mmSTQFN-20 2.0 x 3.0 mm Documentation
SLG46538 ASM Dual Supply 17 1.8 - 5.0 1.8 - VDD1 - 4 0 7 17 8 16-stage 1 Conf. OSC RC OSC Crystal OSC I²C STQFN-20 2.0 x 3.0 mm MSTQFN-22 2.0 x 2.2 mm Documentation
SLG46537 ASM 18 1.8 - 5.0 - 4 0 7 17 8 16-stage 1 Conf. OSC RC OSC Crystal OSC I²C STQFN-20 2.0 x 3.0 mmMSTQFN-22 2.0 x 2.2 mm Documentation
SLG46536 - 12 1.8 - 5.0 - 3 0 7 25 15 16-stage 1 Conf. OSC Ring OSC Crystal OSC I²C STQFN-14 2.0 x 2.2 mm Documentation
SLG46535 ASM Dual Supply 11 1.8 - 5.01.8 - VDD1 - 3 0 7 17 8 16-stage 1 Conf. OSC Ring OSC Crystal OSC I²C STQFN-14 2.0 x 2.2 mm Documentation
SLG46534 ASM 12 1.8 - 5.0 - 3 0 7 17 8 16-stage 1 Conf. OSC RC OSC Crystal OSC I²C STQFN-14 2.0 x 2.2 mm Documentation
SLG46170 - 12 1.8 - 5.0 - 0 0 8 17 6 16-stage 1 RC OSC - STQFN-14 2.0 x 2.2 mm Documentation
SLG46169 - 12 1.8 - 5.0 - 2 0 7 18 6 16-stage 1 RC OSC - STQFN-14 2.0 x 2.2 mm Documentation
SLG46108 - 6 1.8 - 5.0 - 0 0 4 10 4 8-stage 1 RC OSC - STQFN-8 1.0 x 1.2 mm Documentation
SLG46121 Dual Supply 9 1.8 - 5.01.8 - VDD1 - 2 0 4 16 8 8-stage 1 RC OSC - STQFN-12 1.6 x 1.6 mm Documentation
SLG46621 Dual Supply 17 1.8 - 5.0 1.8 - VDD1 8-bit 6 3 10 26 12 16-stage 2 2 LF OSC Ring OSC RC OSC SPI STQFN-20 2.0 x 3.0 mm Documentation
SLG46620 - 18 1.8 - 5.0 8-bit 6 3 10 26 12 16-stage 2 2 LF OSC Ring OSC RC OSC SPI STQFN-20 2.0 x 3.0 mm Documentation
SLG46117 1x P-FET 7 1.8 - 5.0 - 2 0 4 10 4 8-stage 1 RC OSC - STQFN-14 1.6 x 2.5 mm Documentation
SLG46116 1x P-FET 7 1.8 - 5.0 - 2 0 4 10 4 8-stage 1 RC OSC - STQFN-14 1.6 x 2.5 mm Documentation
SLG46140 - 12 1.8 - 5.0 8-bit 2 3 4 16 6 16-stage 1 LF OSC Ring OSC RC OSC SPI STQFN-14 1.6 x 2.0 mm Documentation
SLG46120 - 10 1.8 - 5.0 - 2 0 4 16 8 8-stage 1 RC OSC - STQFN-12 1.6 x 1.6 mm Documentation
SLG46110 - 8 1.8 - 5.0 - 2 0 4 10 4 8-stage 1 RC OSC - STQFN-12 1.6 x 1.6 mm Documentation
SLG46722 - 18 1.8 - 5.0 - 0 0 8 17 6 16-stage 1 RC OSC - STQFN-20 2.0 x 3.0 mm Documentation
SLG46721 - 18 1.8 - 5.0 - 4 0 7 18 6 16-stage 1 RC OSC - STQFN-20 2.0 x 3.0 mm Documentation
SLG46824 In-System Programmability Dual Supply 17 2.5 - 5.0 1.8 - VDD1 - 2 - 8 19 17 16-stage 1 RC OSC LP OSC Ring OSC I²C STQFN-20 2.0 x 3.0 mm TSSOP-20 6.5 x 6.4 mm Documentation
SLG46826 In-System Programmability Dual Supply 17 2.5 - 5.01.8 - VDD1 - 4 - 8 19 17 16-stage 1 RC OSC LP OSC Ring OSC I²C STQFN-20 2.0 x 3.0 mm TSSOP-20 6.5 x 6.4 mm Documentation
SLG46880 ASMDual Supply 28 2.5 - 5.02.5 - VDD1 - 4 - 5 12 5 16-stage 1 RC OSC LP OSC Ring OSCCrystal OSC I²C STQFN-32 4.0 x 4.0 mm Documentation 28
SLG46881 ASMDual Supply 28 2.5 - 5.01.0 - 1.8 - 4 - 5 12 5 16-stage 1 RC OSC LP OSC Ring OSC Crystal OSC I²C STQFN-32 4.0 x 4.0 mm Documentation
SLG46517 ASM2x P-FET 16 1.8 - 5.0 - 4 - 7 17 8 16-stage 1 RC OSC Ring OSC Crystal OSC I²C MSTQFN-32 2.0 x 3.0 mm Documentation

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