Sending a Preset Number of Pulses

Sending a Preset Number of Pulses

Communication Protocols Technique

This technique can be done in any GreenPAK. Multi-function blocks within some GreenPAKs help reduce the component count.

In many communication protocols it’s necessary for a set number of bits to be sent or received by another IC. Typically, this means the GreenPAK must track the number of pulses sent or received. For example, in a shift register receiving data, the number of bits must be monitored to ensure that the expected data is in the correct register, rather than skewed incorrectly or unrelentingly continuing to shift.

There are many ways to set a predetermined number of pulses in GreenPAK: a scaleable, efficient way is described in this technique. It also has the added benefit of limiting clock skew between the other IC and the GreenPAK by resetting the clock skew after every transaction. Figure 23 shows a pipeline of blocks for creating a preset number of pulses. It consists of: Turnon Condition, Pulse Period, and a Pulse Counter.

Figure 23 Preset Pulse Generator Design

The Turnon Condition stage has two components: a DLY block to ensure a minimum active signal to begin the pulse generation and a LUT to ensure the turnon condition isn’t re-instantiated before the last transaction has completed. Depending upon the application this stage may not be necessary.

The Pulse Period stage has two elements: a DFF and a counter. The DFF will disable the RESET_IN signal of the counter when the turnon condition is met. It will stay low until the pulse count has finished. The counter is used to set the period of the discrete pulses and can be configured to match the application.

The Pulse Count stage has a falling-edge delay and a logic gate. The delay’s CLK is connected to the counter in the pulse period stage, which causes it to track the number of pulses. The DLY IN of the delay is connected to the DFF in the Pulse Period stage. This causes the delay to fall low after a set number of pulses, resetting the DFF and halting the shift clock.

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