Optimizing CNT/DLY Accuracy

Optimizing CNT/DLY Accuracy

Timing Functions Technique

This technique works with any GreenPAK. The accuracy of the oscillator and CNT/DLY blocks vary from part-to-part.

GreenPAK ICs, like all chips with internal oscillators, have inherent variation in timing. This is attributed to factors like manufacturing, temperature and, in the case of GreenPAK, user design practices. By using simple design rules, the accuracy of counters and delays within a GreenPAK design can be improved.

The relationship between the oscillators and CNT/DLY blocks should be considered. The oscillators are global oscillators; they can be used for any number of CNT/DLY blocks and aren’t initially synchronized to the start/stop of a delay or counter. Consequently, when a counter or delay is enabled it will only begin to increment on the next clock edge. This is depicted in Figure 9, where an enable signal for a delay is activated mid-clock-cycle and doesn’t begin to decrement until the next rising edge.

Figure 9 Behavior of Rising Enable for Delay

This is factored into the typical delay time calculation for the CNT/DLY blocks:

Thus, as the value of “Counter_Data” increases, the influence of “t” on the delay time will be proportionately less. Additionally, the absolute value of the delay time can be kept the same, despite using a larger “Counter_Data” value, if a faster “clock” value is used. In the Properties window of the selected CNT/DLY block both the Counter Data value and the clock source can be modified.


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