Duty Cycle Detection

Duty Cycle Detection

Pulse-based Control Technique

This technique can be used within any GreenPAK. Since the input frequency range is limited by the maximum FSM counter data, it is better to use a 16-bit FSM. The PWM detection input frequency should be much slower than the duty cycle reference frequency to improve the accuracy.

Duty cycle detection is important for applications such as overload protection, DC/DC conversion, servo motor control, and protocol detection. This design can be easily implemented using a GreenPAK with an FSM block (For the below example a SLG46826 chip is used, see Figure A). 

In the implementation shown above, when PIN#4 goes HIGH, FSM0 starts counting DOWN, clocked by the internal oscillator. FSM0 is set to 65535 by a rising edge on PIN#4. When PIN#4 goes LOW, FSM0 starts counting UP with the frequency from internal oscillator divided by CNT1’s data value (Figure B).  If FSM0 reaches 65535, DFF3 will be set LOW by the next edge rising edge from PIN#04, which flags that the duty cycle is below the set threshold.

                The duty cycle reference frequency can be adjusted by changing the CNT1 counter data value via I2C. To calculate the duty cycle threshold, the following formula is used:



GreenPAK Designer files