Synchronous state machines (SSM) do transitions on the edge of an incoming clock if the transition condition is met. The generic approach to convert an ASM into a SSM uses a clock signal with a pulse width greater than the ASM transition time.

Consider the SSM in the 3-bit counter example above. CNT2 and 2-bit LUT1 are used to generate the clock. The ASM uses 8 states connected in series. 2-bit LUT0 and 2-bit LUT3 are used to prevent a logic high signal on two near state transitions. The value of the ASM output for every state is shown below.

The ASM changes from the reset state (State 0) to the next state (State 1) when PIN6 goes high. The following transitions through the states occur as CNT2 toggles first high, then low, and so on.

For more a detailed information about the process of creating an SSM with the ASM see AN-1126 ASM to Synchronous Conversion.

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