Creating a Bidirectional Counter

Creating a Bidirectional Counter

Signal Conditioning Technique

This technique can be used within any GreenPAK that includes a SPI interface. Alternatives to this technique can be accomplished using other GreenPAKs with an FSM block and storing the counter information using an I2C read command, parallel output, or other method.

A Counter is a basic digital circuit used for counting input events (pulses, edges), often constructed using a cascade of digital flip-flops. In GreenPAK some CNT/DLY blocks are more robust, and can be used as a finite state machine (FSM) that is not only capable of incrementing but can decrement or hold the current value, dictated by interconnects in the GreenPAK matrix. This technique exemplifies this behaviour by using two FSM blocks in GreenPAK to monitor a pulse input (Clock) and output the corresponding 16-bit sequence via the SLG46140V’s SPI macrocell.

The “16-bit FSM with SPI output” counts input clock pulses in a constructed 16-bit register (FSM0, FSM1). At any time a user can read the value via SPI, reset the 16-bit register, or change the count direction.

The 16-bit counter is implemented using two counters (FSM0 and FSM1 blocks) with additional logic. Bits [15:8] are stored in FSM0, Creating a Bidirectional Counter in FSM1. Both FSMs are connected to the SPI block, which can output serial data via SPI. The count direction is controlled by an Up/Down pin, directly connected to the FSM blocks’ UP matrix output. If this pin is HIGH, the system counts UP, if this pin is LOW, the system counts DOWN. Gen Reset pin is used to reset both counter values (active HIGH).

The Clock input pin is applied simultaneously at the CLK input of FSM1 and FSM0. FSM1 counts each clock, whereas FSM0 counts only when FSM1 counter value is 255 and Up/Down signal is HIGH or when FSM1 counter value is 0 and Up/Down signal is LOW. This functionality is achieved using the KEEP input of the FSM0. When this signal is HIGH the counter value of the FSM0 is not changing despite the clock signal. KEEP is connected to FSM1 output through an inverter. In turn, FSM1’s output is only HIGH when counter value is 0 and Up/Down signal is LOW, or when counter value is 255 and Up/Down signal is HIGH.

 

Resources

GreenPAK Designer files