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AN-1109 Four-level Voltage Comparison with Single Comparator in GreenPAK

Contents

References

For related documents and software, please visit:

https://www.dialog-semiconductor.com/products/greenpak

Download our free GreenPAK Designer software [1] to open the .gp file [2] and use the GreenPAK development tools [3] to freeze the design into your own customized IC in a matter of minutes.

Dialog Semiconductor provides a complete library of application notes [4] featuring design examples as well as explanations of features and blocks within the Dialog IC.

  1. GreenPAK Designer Software, Software Download, and User Guide, Dialog Semiconductor
  2. AN-1109 Four-level voltage comparison with single comparator in GreenPAK.gp, GreenPAK Design File, Dialog Semiconductor
  3. GreenPAK Development Tools, GreenPAK Development Tools Webpage, Dialog Semiconductor
  4. GreenPAK Application Notes, GreenPAK Application Notes Webpage, Dialog Semiconductor
  5. SLG46120 Datasheet, Dialog Semiconductor

Author: Yu-Han Sun

Introduction

The SLG46120V [5] is a versatile, programmable, configurable, small and low cost device. To minimize cost and size, the SLG46120V does not include an ADC. For applications that only require a few levels of comparison, we can make a 2-bit ADC, or 4 level comparator using just some of the resources of Dialog’s 1.6 x 1.6mm SLG46120V GreenPAK.

Application

An example application is a battery monitor with a state of charge indicator as shown in Figure 1. The 2-bit ADC will determine battery level and light a series of output LEDs. Four lit LEDs indicate a fully charged battery and zero lit LEDs indicate a discharged battery.

Figure 1. System Level View

A 4.2V battery is interfaced by a PMIC, which creates a linear representation of the battery voltage from 0V to 1V. 1V means the battery is fully charged and 0V means the battery is fully discharged.

This linearized voltage is then fed into the 2-bit ADC, comprised of a 2-bit DAC and the GreenPAK analog comparator. If the 2-bit DAC is greater, the output of the analog comparator is HIGH. After checking all four DAC levels, the GreenPAK will drive the LEDs which indicate battery voltage.

The PMIC, GreenPAK and DAC are powered by an LDO. The LDO is needed to make sure the 2-bit DAC reference voltages are stable.

GreenPAK Design

An ADC compares a target voltage (linearized battery voltage) to a reference voltage generated by a DAC. In this application, we will use an Analog Comparator to compare the external DAC with the target voltage.

The DAC is a 2-bit resistor network where the resistors are pulled up or down in different combinations to divide the LDO into different voltages. These voltages enter the Analog Comparator on IN+ as the reference voltage.

The pull up and pull down state of the resistors are set by two binary signals: PIN#5 (MSB) and PIN#8 (LSB). The signals are generated by the OSC as shown in Figure 2. The sample rate is OSC/48.

The ACMP output is connected to four DFFs (DFF0, 1, 2, and 3) which latch and hold the ACMP output.

Figure 2. Timing Diagram

The DFFs are clocked one after the other by a time multiplexed signal. This signal is generated by the combinational logic of the MSB, LSB and OSC/12. We use OSC/12 to make sure the ACMP output has stabilized before the DFFs are clocked. Figure 2 shows the time multiplexed clock signals generated by the 3-bit LUTs 4, 5, 6 and 7.

Each DFF drives an LED on PINs 12, 11, 10 and 9. As the battery voltage increases, the number of LEDs lit will also increase.

Figure 3. ACMP0 Properties

Analog Comparator Settings

The Analog Comparator IN+ is the DAC reference voltage. An optional IN+ gain can be used to divide the reference down to 1V if it is not already.

Figure 4. GreenPAK Designer Project View

The IN- source comes from the PMIC through PIN#4. It is important to note that PIN#4 should not exceed 1.2V. Refer to the datasheet section 5.0 for limits at different VDDs.

Resistor Network Scheme #1

The first resistor network uses a R/2R resistor ladder and pulls two resistors up or down to get four different combinations. If the resistors are selected in accordance to the formulas below, all thresholds will be evenly spaced, and the input impedance is set by R. Since the GPIOs can only drive to GND or VDD, you will need another divider stage to scale the reference to 1V.

In our application where VDD is 3.0V, we are able to use the 0.33x input gain stage of the ACMP to divide 3.0V by three. Otherwise, external voltage dividers must be used.

R1 = 2*R

R2 = 2*R

R3 = R

R4 = 2*R

Input impedance is a parallel combination of R and the gain stage. Refer to datasheet section 13.0. The 0.33x gain has input impedance of 0.75MΩ.

Figure 5. Resistor Network Schematic #1

In Figure 5, the bottom side of resistors R2 and R4 are controlled by PIN#5 (MSB) and PIN#8 (LSB). These two pins represent the binary bits b1 and b0 as described in Table 1. Table 1 lists the expected DAC reference voltage at the PIN#3 input if VDD is 3000mV.

Table 1. b1 and b0 to DAC voltage

PIN#5 (b1)

PIN#8 (b0)

PIN#3

0

0

750mV

0

1

1500mV

1

0

2250mV

1

1

3000mV

If we use the 0.33x internal gain divider of the ACMP, the expected IN+ voltage is listed in Table 2.

Table 2. ACMP IN+ voltage

PIN#3

0.33x

750mV

250mV

1500mV

500mV

2250mV

750mV

3000mV

1000mV

Resistor Network Scheme #2

A second resistor network that can be used is a resistor pull down-only layout. Unlike the previous design, this one only pulls down instead of pulling resistors both up and down. Outputs PIN#5 and PIN#8 are ODNMOS. This automatically keeps the voltages under 1V, eliminating need for a second divider stage. However, due to lack of flexibility, the resulting thresholds are non-linear. See Table 3 and Figure 6 below.

R1 = 10000

R2 = 4348

R3 = 6559

R4 = 2249

Figure 6. Resistor Network Schematic #2

The percent error for this set of resistors, if the expected values are 250, 500, 750 and 1000mV, is 14.511%.

See Appendix A for an octave script which finds the resistor values that result in the least percent error from the expected values and desired input impedance. It also includes a weight parameter to add weight to certain values if desired. For this example, all variables hold equal weight. The output of the octave code is shown below where xx, yy and zz are the DAC voltages in volts, entered into Table 3.

Table 3. b1 and b0 to DAC Voltage

PIN#5 (b1)

PIN#8 (b0)

PIN#3

0

0

356mV

0

1

426mV

1

0

680mV

1

1

1000mV

Figure 7. Device Functionality (ZOOM) for Resistor Network Schematic #1

Functionality Waveforms

D0 – PIN#12 (LED4)

D1 – PIN#11 (LED3)

D2 – PIN#10 (LED2)

D3 – PIN#9 (LED1)

Channel 1 (yellow) – PIN#3 (DAC)

Channel 3 (magenta) – PIN#4 (PMIC_In)

Figure 8. Device Functionality for Resistor Network Schematic #1

Conclusion

The 2-bit ADC, or four level Analog Comparator, works for applications that only need a coarse set of thresholds. With a few external resistors and some control logic, the SLG46120V can do just that. Select the best resistor network that suits the system. If the concern is cost and the internal gain dividers do not suffice, the first resistor schematic leaves you with six external resistor components. In this case, the second resistor schematic may be more cost efficient, requiring only four external resistors but the threshold accuracy decreases.

More than four levels would require another output pin to control the next most significant bit in the binary selection, but there aren’t enough outputs to control 8 LEDs. A 3-bit ADC could be implemented in a SLG46721V, which has more GPIO and also does not have a built-in ADC.

Appendix A. Resistor Calculation (Octave)