DA9036: Highly-integrated analogue front-end with RF interface for WCDMA phones

Dialog Semiconductor’s DA9036 is a highly integrated analog front end solution for WCDMA phones. Designed to provide data conversion of both transmit and receive RF channels the part integrates high speed precision data converters which are matched to provide identical gain and phase error performance.

The receive chain takes differential I/Q signals and performs low pass filtering to precondition the ADC inputs and remove high frequency components. The paths are AC coupled to remove external DC offsets and also have DC compensation to cancel internally generated offsets. The I and Q signals are then fed to two 8 bit ADC’s. The conversion results are then multiplexed and fed out over an 8 bit parallel interface.

The transmit chain consists of 10 bit parallel data input and synchronisation buffer , two high speed 10 bit DACs followed by a 5th order low pass filters(3.5MHz bandwidth) and programmable gain stages. The transmit signal chain is designed for low phase and group delay mismatch.

These main RF converters are supported by low power monitoring converters used for measurement and control.

Three DAC channels are provided: the DAC outputs may be updated upon receiving new data or can have the voltage change synchronized to an external strobe signal.

Complementing the DAC’s is a 10 bit ADC with a 3 channel input multiplexer. The ADC may be configured for single or continuous conversions with measurements being taken immediately if controlled by an external strobe. In continuous mode the converter will make measurements every 168/84 clock cycles. The ADC also includes a programmable averaging feature, the user can select the number of measurements to be averaged and an interrupt is generated on completion and the result stored in a register location.

The DA9036 has a 5 pin GPIO expansion port for interfacing to external circuits. When configured as outputs the pins respond immediately to changes in the GPIO registers.

Designed for low power operation inactive blocks may be powered down to minimize current consumption.

Overview

Receive I/Q path

Differential architecture for enhanced noise immunity
8 bit resolution with 15.36MHz conversion rate.
Better than 1° phase mismatch, 0.2db gain mismatch between channels.
THD at pass band -47dBc max
Crosstalk better than 50dB minimum at full scale input signal

Transmit I/Q path

LPF pass band DC to 1.92 Mhz
10 bit resolution with 15.36MHz conversion rate
Better than 1° phase mismatch, 0.3db gain mismatch between channels.
THD at pass band -48dBc max
Output signals up to 1.5Vpkpk supported

General purpose ADC

3 channel analog multiplexer with 70dB isolation between channels.
40KHz maximum conversion rate
10 bit +/-1LSB differential linearity

General purpose DACs

3 independent very low DAC channels
2KHz conversion rates, 5µs settling
10 bit +2/-1LSB differential linearity, 2 x 11 bit +/-1LSB differentiallinearity

Package

64BGA 5 by 5 by 1mm, 0.5mm pitch